--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -7986,6 +7986,8 @@
       if (MEM_ALIGN (src) == BITS_PER_WORD / 2
 	  && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
 	bits = BITS_PER_WORD / 2;
+      else if (TARGET_LEXRA)
+        bits = MIN (MEM_ALIGN (src), MEM_ALIGN (dest));
       else
 	bits = BITS_PER_WORD;
     }
@@ -8361,6 +8363,8 @@
     }
   else
     {
+      if (TARGET_LEXRA)
+        return false;
       emit_insn (gen_mov_lwl (temp, src, left));
       emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
     }
@@ -8404,6 +8408,8 @@
     }
   else
     {
+      if (TARGET_LEXRA)
+        return false;
       emit_insn (gen_mov_swl (dest, src, left));
       emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
     }
@@ -19663,6 +19669,10 @@
   if (mips_arch_info == 0)
     mips_set_architecture (mips_default_arch ());
 
+  /* flag_fix_bdsl only works for Taroko processors */
+  if (flag_fix_bdsl && !TARGET_LEXRA)
+    flag_fix_bdsl = false;
+
   if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
     error ("%<-march=%s%> is not compatible with the selected ABI",
 	   mips_arch_info->name);
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -286,6 +286,7 @@
 				     || mips_arch == PROCESSOR_SB1A)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
 #define TARGET_XLP                  (mips_arch == PROCESSOR_XLP)
+#define TARGET_LEXRA		    (mips_arch == PROCESSOR_LEXRA)
 
 /* Scheduling target defines.  */
 #define TUNE_20KC		    (mips_tune == PROCESSOR_20KC)
@@ -299,7 +300,7 @@
 #define TUNE_LOONGSON_2EF           (mips_tune == PROCESSOR_LOONGSON_2E	\
 				     || mips_tune == PROCESSOR_LOONGSON_2F)
 #define TUNE_LOONGSON_3A            (mips_tune == PROCESSOR_LOONGSON_3A)
-#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
+#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000 || TUNE_LEXRA)
 #define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
 #define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
 #define TUNE_MIPS4120               (mips_tune == PROCESSOR_R4120)
@@ -317,6 +318,7 @@
 				     || mips_tune == PROCESSOR_SB1A)
 #define TUNE_P5600                  (mips_tune == PROCESSOR_P5600)
 #define TUNE_I6400                  (mips_tune == PROCESSOR_I6400)
+#define TUNE_LEXRA		    (mips_tune == PROCESSOR_LEXRA)
 
 /* Whether vector modes and intrinsics for ST Microelectronics
    Loongson-2E/2F processors should be enabled.  In o32 pairs of
@@ -641,6 +643,13 @@
 	builtin_define ("__mips_no_lxc1_sxc1");				\
       if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4)		\
 	builtin_define ("__mips_no_madd4");				\
+									\
+      if (TARGET_LEXRA)							\
+	builtin_define ("__mlexra");					\
+									\
+      if (flag_fix_bdsl)						\
+	builtin_define ("__FIX_BDSL__");				\
+									\
     }									\
   while (0)
 
@@ -799,7 +808,8 @@
   "%{mhard-float|msoft-float|mno-float|march=mips*:; \
      march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
      |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
-     |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
+     |march=m14k*|march=m5101|march=octeon|march=xlr \
+     |march=lexra: -msoft-float; \
      march=*: -mhard-float}"
 
 /* A spec condition that matches 32-bit options.  It only works if
@@ -1105,7 +1115,7 @@
 				      && (MODE) == V2SFmode))		\
 				 && !TARGET_MIPS16)
 
-#define ISA_HAS_LWL_LWR		(mips_isa_rev <= 5 && !TARGET_MIPS16)
+#define ISA_HAS_LWL_LWR		(mips_isa_rev <= 5 && !TARGET_MIPS16 && !TARGET_LEXRA)
 
 #define ISA_HAS_IEEE_754_LEGACY	(mips_isa_rev <= 5)
 
@@ -1396,6 +1406,7 @@
 
 #undef CC1_SPEC
 #define CC1_SPEC "\
+%{mlexra:-march=lexra} \
 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
 %(subtarget_cc1_spec)"
 
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -69,6 +69,7 @@
   p5600
   m5100
   i6400
+  lexra
 ])
 
 (define_c_enum "unspec" [
@@ -757,9 +758,13 @@
 
 ;; Can the instruction be put into a delay slot?
 (define_attr "can_delay" "no,yes"
-  (if_then_else (and (eq_attr "type" "!branch,call,jump")
-		     (eq_attr "hazard" "none")
-		     (match_test "get_attr_insn_count (insn) == 1"))
+  (if_then_else (and (ior (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+			  (eq (symbol_ref "flag_fix_bdsl") (const_int 0)))
+		     (ior (eq_attr "type" "!load")
+			  (eq (symbol_ref "flag_fix_bdsl") (const_int 0)))
+		     (and (eq_attr "type" "!branch,call,jump")
+			  (eq_attr "hazard" "none")
+		 	  (match_test "get_attr_insn_count (insn) == 1")))
 		(const_string "yes")
 		(const_string "no")))
 
@@ -4339,7 +4344,7 @@
 	(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
 		     (match_operand:QI 2 "memory_operand" "ZC")]
 		    UNSPEC_LOAD_LEFT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
   "<load>l\t%0,%2"
   [(set_attr "move_type" "load")
    (set_attr "mode" "<MODE>")])
@@ -4350,7 +4355,7 @@
 		     (match_operand:QI 2 "memory_operand" "ZC")
 		     (match_operand:GPR 3 "register_operand" "0")]
 		    UNSPEC_LOAD_RIGHT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
   "<load>r\t%0,%2"
   [(set_attr "move_type" "load")
    (set_attr "mode" "<MODE>")])
@@ -4360,7 +4365,7 @@
 	(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
 		     (match_operand:QI 2 "memory_operand" "ZC")]
 		    UNSPEC_STORE_LEFT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
   "<store>l\t%z1,%2"
   [(set_attr "move_type" "store")
    (set_attr "mode" "<MODE>")])
@@ -4371,7 +4376,7 @@
 		     (match_operand:QI 2 "memory_operand" "ZC")
 		     (match_dup 0)]
 		    UNSPEC_STORE_RIGHT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
   "<store>r\t%z1,%2"
   [(set_attr "move_type" "store")
    (set_attr "mode" "<MODE>")])
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -315,6 +315,10 @@
 Target Report Var(TARGET_MCU)
 Use MCU instructions.
 
+mno-bdsl
+Target Report Var(flag_fix_bdsl) Init(0)
+Forbid the use of load instructions in the branch delay slots for all cases
+
 mno-flush-func
 Target RejectNegative
 Do not use a cache-flushing function before calling stack trampolines.
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -171,3 +171,6 @@
 
 /* MIPS64 Release 6 processors.  */
 MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0)
+
+/* Lexra processors */
+MIPS_CPU ("lexra", PROCESSOR_LEXRA, 1, 0)
--- a/gcc/config/mips/mips-tables.opt
+++ b/gcc/config/mips/mips-tables.opt
@@ -696,3 +696,6 @@
 EnumValue
 Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical
 
+EnumValue
+Enum(mips_arch_opt_value) String(lexra) Value(103) Canonical
+
